Yuki Fujimura

A 0.7 V Single-Supply SRAM With 0.495 $\mu$m$^{2}$ Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme

K. Kushida, Azuma Suzuki, Gou Fukano et al. · IEEE Journal of Solid-State Circuits · 2009 · 52 citations

Engineering, Computer Engineering, Electrical Engineering +17

A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm<sup>2</sup> cell in 32nm high-<inf>k</inf> metal-gate CMOS

Yuki Fujimura, Osamu Hirabayashi, Takahiko Sasaki et al. · 2010 · 46 citations

Engineering, Computer Engineering, Electrical Engineering +15

A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers

Yusuke Niki, Atsushi Kawasumi, Azuma Suzuki et al. · IEEE Journal of Solid-State Circuits · 2011 · 38 citations

Engineering, Computer Engineering, Electrical Engineering +15

An 802.11ax 4 <inline-formula> <tex-math notation="LaTeX">$\times$ </tex-math> </inline-formula> 4 High-Efficiency WLAN AP Transceiver SoC Supporting 1024-QAM With Frequency-Dependent IQ Calibration and Integrated Interference Analyzer

Shusuke Kawai, Rui Ito, Kengo Nakata et al. · IEEE Journal of Solid-State Circuits · 2018 · 20 citations

Engineering, Computer Engineering, Electrical Engineering +17

A Low-Supply-Voltage-Operation SRAM With HCI Trimmed Sense Amplifiers

Atsushi Kawasumi, Y. Takeyama, Osamu Hirabayashi et al. · IEEE Journal of Solid-State Circuits · 2010 · 14 citations

Engineering, Computer Engineering, Electrical Engineering +17