Y. Takeyama

A process-variation-tolerant dual-power-supply SRAM with 0.179µm<sup>2</sup> Cell in 40nm CMOS using level-programmable wordline driver

Osamu Hirabayashi, Atsushi Kawasumi, Akira Suzuki et al. · 2009 · 92 citations

Low-power Electronics, Level-programmable Wordline Driver, Electrical Engineering +10

A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS

Cuong Trinh, Noboru Shibata, Takumi Nakano et al. · 2009 · 69 citations

Non-volatile Memory, Engineering, Technology Scaling +13

A 0.7 V Single-Supply SRAM With 0.495 $\mu$m$^{2}$ Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme

K. Kushida, Azuma Suzuki, Gou Fukano et al. · IEEE Journal of Solid-State Circuits · 2009 · 52 citations

Low-power Electronics, Electrical Engineering, Novel Sram Architecture +10

Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm Node and Beyond

Hikaru Kawasaki, K. Okano, A. Kaneko et al. · 2006 · 44 citations

Electrical Engineering, Engineering, Vlsi Design +12

A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm<sup>2</sup> cell in 32nm high-<inf>k</inf> metal-gate CMOS

Yuki Fujimura, Osamu Hirabayashi, Takahiko Sasaki et al. · 2010 · 44 citations

Non-volatile Memory, Electrical Engineering, Metal-gate Cmos +13