A process-variation-tolerant dual-power-supply SRAM with 0.179µm<sup>2</sup> Cell in 40nm CMOS using level-programmable wordline driver

Osamu Hirabayashi, Atsushi Kawasumi, Akira Suzuki, +10

Low-power ElectronicsLevel-programmable Wordline DriverElectrical EngineeringProcess-variation-tolerant Dual-power-supply SramKb Dual-power-supply Sram +8

A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS

Cuong Trinh, Noboru Shibata, Takumi Nakano, +52

Non-volatile MemoryEngineeringTechnology ScalingFlash MemoryComputer Engineering +11

A 0.7 V Single-Supply SRAM With 0.495 $\mu$m$^{2}$ Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme

K. Kushida, Azuma Suzuki, Gou Fukano, +7

IEEE Journal of Solid-State Circuits

Low-power ElectronicsElectrical EngineeringNovel Sram ArchitectureEngineeringVlsi Design +8

Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm Node and Beyond

Hikaru Kawasaki, K. Okano, A. Kaneko, +15

Electrical EngineeringEngineeringVlsi DesignStatic Noise MarginHp32 Nm Node +10

A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm<sup>2</sup> cell in 32nm high-<inf>k</inf> metal-gate CMOS

Yuki Fujimura, Osamu Hirabayashi, Takahiko Sasaki, +8

Non-volatile MemoryElectrical EngineeringMetal-gate CmosEngineeringVlsi Design +11

A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers

Yusuke Niki, Atsushi Kawasumi, Azuma Suzuki, +6

IEEE Journal of Solid-State Circuits

Low-power ElectronicsRandom-variation-tolerant Timing GenerationElectrical EngineeringEngineeringVlsi Design +13

A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-ß-ratio Memory Cell

Atsushi Kawasumi, Tomoaki Yabe, Y. Takeyama, +8

Low-power ElectronicsElectrical EngineeringBulk SramVlsi DesignEngineering +10

A Low Leakage SRAM Macro With Replica Cell Biasing Scheme

Y. Takeyama, Hiroyuki Otake, Osamu Hirabayashi, +2

IEEE Journal of Solid-State Circuits

Hardware SecurityNon-volatile MemoryElectrical EngineeringEngineeringReplica Cell +8

13.4 A 7ns-access-time 25μW/MHz 128kb SRAM for low-power fast wake-up MCU in 65nm CMOS with 27fA/b retention current

Toshikazu Fukuda, Koji Kohara, Toshiaki Dozaka, +6

EngineeringVlsi DesignMemory DesignEnergy EfficiencyComputer Architecture +18

A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit

Fumihiko Tachibana, Osamu Hirabayashi, Y. Takeyama, +8

IEEE Journal of Solid-State Circuits

Low-power ElectronicsActive ModeElectrical EngineeringPower-aware ComputingEngineering +8