Ali Farhang

Wordline & Bitline Pulsing Schemes for Improving SRAM Cell Stability in Low-Vcc 65nm CMOS Designs

Muhammad Khellah, Y. Ye, N. Kim et al. · 2006 · 85 citations

Engineering, Computer Engineering, Electrical Engineering +8

A 256-Kb Dual-${V}_{\rm CC}$ SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor

Muhammad Khellah, Dinesh Somasekhar, Yibin Ye et al. · IEEE Journal of Solid-State Circuits · 2007 · 58 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 4.2GHz 0.3mm2 256kb Dual-V/sub cc/ SRAM Building Block in 65nm CMOS

Muhammad Khellah, Nam Sung Kim, Jason Howard et al. · 2006 · 31 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 6-GHz 16-kB L1 cache in a 100-nm dual-v t technology using a bitline leakage reduction (blr) technique

Yibin Ye, Muhammad Khellah, Dinesh Somasekhar et al. · IEEE Journal of Solid-State Circuits · 2003 · 21 citations

Engineering, Computer Engineering, Electrical Engineering +17