Cache Leakage Reduction

Cache Leakage Reduction is a methodological approach in low-power cache design that specifically targets the minimization of static power consumption due to subthreshold leakage currents in cache memory structures by employing circuit, architecture, or management techniques that reduce idle-state energy dissipation.

177

Publications

11K

Citations

460

Authors

102

Institutions

Publications per year

2017–2026

11

Authors

460

  1. KR
    Kaushik Roy

    Purdue University West Lafayette, United States

    12 publications · 1.6K citations

    12

    h-index

  2. NS
    Nam Sung Kim

    University of Illinois Urbana-Champaign, United States

    11 publications · 1.7K citations

    11

    h-index

  3. VD
    Vivek De

    Intel (United States), United States

    9 publications · 767 citations

    9

    h-index

  4. SR
    Stefan Rusu

    Intel (United States), United States

    9 publications · 458 citations

    9

    h-index

  5. DB
    David Blaauw

    University of Michigan, United States

    8 publications · 1.6K citations

    8

    h-index

1–5 of 460

Venues

  1. 13

    h-index

  2. IEEE Journal of Solid-State Circuits

    10 publications · 614 citations

    10

    h-index

  3. ACM Transactions on Architecture and Code Optimization

    TACO · 6 publications · 205 citations

    6

    h-index

  4. IEEE Transactions on Computers

    4 publications · 103 citations

    4

    h-index

  5. ACM Transactions on Embedded Computing Systems

    TECS · 3 publications · 116 citations

    3

    h-index

1–5