Cache Leakage Reduction
Cache Leakage Reduction is a methodological approach in low-power cache design that specifically targets the minimization of static power consumption due to subthreshold leakage currents in cache memory structures by employing circuit, architecture, or management techniques that reduce idle-state energy dissipation.
177
Publications
11K
Citations
460
Authors
102
Institutions
Publications per year
2017–2026
11
Parents
177
Krisztián Flautner, Nam Sung Kim, Steve Martin et al. · ACM SIGARCH Computer Architecture News · 2002 · 742 citations
Michael D. Powell, Se-Hyun Yang, Babak Falsafi et al. · 2000 · 669 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +17
Stefanos Kaxiras, Zhigang Hu, Margaret Martonosi · 2001 · 613 citations
Drowsy caches: simple techniques for reducing leakage power
Krisztián Flautner, Nam Sung Kim, Steve Martin et al. · 2003 · 347 citations
Scaling of stack effect and its application for leakage reduction
S. Narendra, Vivek De, D.A. Antoniadis et al. · 2001 · 332 citations
1–5 of 177
460
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102
Intel (United States)
Santa Clara, United States
17 h-index
162 publications
8.7K citations
Purdue University West Lafayette
West Lafayette, United States
14 h-index
50 publications
7.1K citations
University of Michigan
Ann Arbor, United States
11 h-index
35 publications
6.1K citations

Pennsylvania State University
State College, United States
11 h-index
47 publications
2.3K citations
University of Virginia
Charlottesville, United States
9 h-index
14 publications
491 citations
University of California, Irvine
Irvine, United States
8 h-index
26 publications
649 citations
Princeton University
Princeton, United States
8 h-index
20 publications
2.9K citations

Sharif University of Technology
Tehran, Iran
5 h-index
18 publications
401 citations
1–8 of 102
17 publications · 859 citations
13
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10 publications · 614 citations
10
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TACO · 6 publications · 205 citations
6
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4 publications · 103 citations
4
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TECS · 3 publications · 116 citations
3
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1–5