Low-power Cache Design
Low-Power Cache Design is a subfield of cache memory architecture that studies and develops circuit- and architecture-level techniques for reducing the dynamic and static energy consumption of cache hierarchies while preserving required performance, capacity, and correctness constraints in integrated systems.
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Publications
63.7K
Citations
3.5K
Authors
594
Institutions
Publications per year
2017–2026
194
Variants
Low-power Design AutomationLow-power Memory DesignLow-power System-on-chip DesignThermal-aware Low-power Design
Parents
1.3K
Zidong Du, Robert Fasthuber, Tianshi Chen et al. · 2015 · 961 citations · Full text
Krisztián Flautner, Nam Sung Kim, Steve Martin et al. · ACM SIGARCH Computer Architecture News · 2002 · 742 citations
R. M. Banakar, Stefan Steinke, Bo-Sik Lee et al. · 2002 · 661 citations
Selective cache ways: on-demand cache resource allocation
David H. Albonesi · 1999 · 601 citations
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Intel (United States)
Santa Clara, United States
40 h-index
441 publications
24.2K citations

Pennsylvania State University
State College, United States
31 h-index
241 publications
12.8K citations
University of Michigan
Ann Arbor, United States
26 h-index
128 publications
16.2K citations
Purdue University West Lafayette
West Lafayette, United States
25 h-index
126 publications
7.8K citations
University of Pittsburgh
Pittsburgh, United States
23 h-index
102 publications
4.9K citations
Universitat Politècnica de Catalunya
Barcelona, Spain
23 h-index
105 publications
4.4K citations
University of California, Irvine
Irvine, United States
20 h-index
98 publications
2.7K citations
Carnegie Mellon University
Pittsburgh, United States
19 h-index
63 publications
8.3K citations
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62 publications · 2.4K citations
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59 publications · 2.6K citations
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38 publications · 2.9K citations
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32 publications · 993 citations
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17 publications · 880 citations
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