Low-power Cache Design

Low-Power Cache Design is a subfield of cache memory architecture that studies and develops circuit- and architecture-level techniques for reducing the dynamic and static energy consumption of cache hierarchies while preserving required performance, capacity, and correctness constraints in integrated systems.

1.3K

Publications

63.7K

Citations

3.5K

Authors

594

Institutions

Publications per year

2017–2026

194

Authors

3.5K

  1. KR
    Kaushik Roy

    Purdue University West Lafayette, United States

    31 publications · 1.8K citations

    23

    h-index

  2. YX
    Yuan Xie

    Pennsylvania State University, United States

    31 publications · 2.2K citations

    22

    h-index

  3. TM
    Trevor Mudge

    University of Michigan, United States

    23 publications · 3K citations

    19

    h-index

  4. MK
    Mahmut Kandemir

    Pennsylvania State University, United States

    20 publications · 894 citations

    16

    h-index

  5. HL
    Hai Li

    University of Pittsburgh, United States

    19 publications · 1.1K citations

    16

    h-index

1–5 of 3.5K

Venues

  1. 27

    h-index

  2. IEEE Journal of Solid-State Circuits

    59 publications · 2.6K citations

    27

    h-index

  3. ACM SIGARCH Computer Architecture News

    38 publications · 2.9K citations

    23

    h-index

  4. IEEE Transactions on Computers

    32 publications · 993 citations

    19

    h-index

  5. IEEE Micro

    17 publications · 880 citations

    15

    h-index

1–5