Concepedia

Cache Dynamic Power Reduction

Cache Dynamic Power Reduction is a methodological contribution in computer architecture that reduces energy consumption during cache operation by minimizing the power expended in charging and discharging bitlines, wordlines, and tag-matching circuits through circuit-level optimizations, access frequency reduction, or selective activation of cache components.

180

Publications

10.5K

Citations

422

Authors

118

Institutions

Publications per year

2017–2026

4

Parents

Publications

180

Drowsy caches

Krisztián Flautner, Nam Sung Kim, Steve Martin et al. · ACM SIGARCH Computer Architecture News · 2002 · 742 citations

, , +17

Cache decay

Stefanos Kaxiras, Zhigang Hu, Margaret Martonosi · 2001 · 613 citations

, , +17

Selective cache ways: on-demand cache resource allocation

David H. Albonesi · 1999 · 601 citations

, , +17

Selective cache ways: on-demand cache resource allocation

David H. Albonesi · 2003 · 366 citations

, , +17

Drowsy caches: simple techniques for reducing leakage power

Krisztián Flautner, Nam Sung Kim, Steve Martin et al. · 2003 · 347 citations

, , +17

1–5 of 180

Authors

422

  1. FV
    Frank Vahid

    University of California, Riverside, United States

    13 publications · 746 citations

    12

    h-index

  2. CZ
    Chuanjun Zhang

    University of California, Riverside, United States

    10 publications · 719 citations

    10

    h-index

  3. KA
    Krste Asanović

    University of California, Berkeley, United States

    8 publications · 574 citations

    8

    h-index

  4. JY
    Jun Yang

    University of Pittsburgh, United States

    7 publications · 557 citations

    7

    h-index

  5. WN
    Walid Najjar

    University of California, Riverside, United States

    7 publications · 515 citations

    7

    h-index

1–5 of 422

Institutions

118

  1. University of California, Riverside

    Riverside, United States

    13 h-index

    40 publications

    2.4K citations

  2. University of California, Irvine

    Irvine, United States

    13 h-index

    36 publications

    979 citations

  3. Intel (United States)

    Santa Clara, United States

    12 h-index

    85 publications

    5.6K citations

  4. Pennsylvania State University

    State College, United States

    8 h-index

    33 publications

    695 citations

  5. University of Illinois Urbana-Champaign

    Urbana, United States

    6 h-index

    21 publications

    1.5K citations

  6. University of Pisa

    Pisa, Italy

    6 h-index

    24 publications

    470 citations

  7. Chalmers University of Technology

    Gothenburg, Sweden

    5 h-index

    8 publications

    281 citations

  8. University of Rochester

    Rochester, United States

    5 h-index

    18 publications

    2.2K citations

1–8 of 118

Venues

  1. ACM SIGARCH Computer Architecture News

    9 publications · 1.2K citations

    9

    h-index

  2. 7

    h-index

  3. IEEE Journal of Solid-State Circuits

    4 publications · 205 citations

    4

    h-index

  4. ACM Transactions on Embedded Computing Systems

    TECS · 3 publications · 145 citations

    3

    h-index

  5. 3

    h-index

1–5