Trends in low-power RAM circuit technologies

K. Itoh, K. Sasaki, Y. Nakagome

Proceedings of the IEEE

Hardware SecurityLow-power ElectronicsElectrical EngineeringNon-volatile MemoryEngineering +10

An experimental 1.5-V 64-Mb DRAM

Y. Nakagome, Hiroki Tanaka, Kazuhiro Takeuchi, +11

IEEE Journal of Solid-State Circuits

Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignHigher-density Dynamic Rams +9

Review and future prospects of low-voltage RAM circuits

Y. Nakagome, Masashi Horiguchi, T. Kawahara, +1

IBM Journal of Research and Development

Non-volatile MemoryEngineeringEmerging Memory TechnologyComputer ArchitectureComputer Memory +15

Frequency-Dependent Switching Behavior under Triangular Waves in Antiferroelectric and Ferrielectric Chiral Smectic Phases

Ji Lee, A. D. L. Chandani, K. Itoh, +3

Japanese Journal of Applied Physics

MultiferroicsOptical MaterialsFerrielectric PhaseEngineeringPhysics +9

Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's

Masashi Horiguchi, T. Sakata, K. Itoh

IEEE Journal of Solid-State Circuits

Low-power ElectronicsElectrical EngineeringSwitched-source-impedance Cmos CircuitEngineeringVlsi Design +12

Temporal and Spatial Behavior of the Field-Induced Transition between Antiferroelectric and Ferroelectric Phases in Chiral Smectics

Masahiro Johno, K. Itoh, Ji Lee, +4

Japanese Journal of Applied Physics

Optical MaterialsEngineeringMultiferroicsFerroelectric ApplicationOptical Properties +20

Sub-1-V swing internal bus architecture for future low-power ULSIs

Y. Nakagome, K. Itoh, M. Isoda, +2

IEEE Journal of Solid-State Circuits

Low-power ElectronicsBus SwingElectrical EngineeringEngineeringVlsi Design +12

Supply voltage scaling for temperature insensitive CMOS circuit operation

A. Bellaouar, A.R. Fridi, Mohammed Elmasry, +1

IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing

Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignCmos Supply Voltage +11

A deep sub-V, single power-supply SRAM cell with multi-V/sub T/, boosted storage node and dynamic load

K. Itoh, A.R. Fridi, A. Bellaouar, +1

Non-volatile MemoryEngineeringVlsi DesignComputer ArchitectureCell Margin +15

Limitations and challenges of multigigabit DRAM chip design

K. Itoh, Y. Nakagome, S. Kimura, +1

IEEE Journal of Solid-State Circuits

Non-volatile MemoryElectrical EngineeringEngineeringMosfet Shallow JunctionNanoelectronics +8