T. Sakata

Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's

Masashi Horiguchi, T. Sakata, K. Itoh · IEEE Journal of Solid-State Circuits · 1993 · 120 citations

Engineering, Electrical Engineering, Circuit Theory +16

A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme

Hitoshi Tanaka, Masakazu Aoki, T. Sakata et al. · IEEE Journal of Solid-State Circuits · 1999 · 57 citations

Engineering, Computer Engineering, Electrical Engineering +17

Subthreshold-current reduction circuits for multi-gigabit DRAM's

T. Sakata, K. Itoh, Masashi Horiguchi et al. · IEEE Journal of Solid-State Circuits · 1994 · 52 citations

Engineering, Computer Engineering, Electrical Engineering +16

An experimental 220 MHz 1 Gb DRAM

Masashi Horiguchi, T. Sakata, Tomonori Sekiguchi et al. · 2002 · 29 citations

Engineering, Computer Engineering, Computer Science +15

A single 1.5-V digital chip for a 10/sup 6/ synapse neural network

Takao Watanabe, K. Kimura, Masahiro Aoki et al. · IEEE Transactions on Neural Networks · 1993 · 28 citations

Engineering, Computer Engineering, Electrical Engineering +17