Subthreshold-current reduction circuits for multi-gigabit DRAM's

Abstract

Two subthreshold-current reduction circuit schemes are described to suppress the increase in current in multi-gigabit DRAM's. One is a hierarchical power-line scheme for iterative circuits. In this scheme, a group of circuits is divided into blocks; only the selected block is supplied with power, while the subthreshold current to the many nonselected blocks is reduced. This scheme minimizes the number of circuits carrying the large subthreshold current. Applications of this scheme to word drivers, decoders and sense-amplifier driving circuits are shown. The other scheme is a switched-power-supply inverter with a level holder for random combinational logic circuits. In the active mode of the chip, the operating period of the inverter is distinguished from the inactive period. The inverter is supplied with power only in the operating period, while in the inactive period the subthreshold current is shut off and the output level is kept by the flip-flop level holder. This scheme shortens the period in which the large subthreshold current flows. Both schemes are evaluated for a conceptually-designed 16-Gb DRAM. They reduce its active current by ten-fold from the conventional 1.2 A to 116 mA.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>