A 0.9-V, 150-MHz, 10-mW, 4 mm/sup 2/, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme

Tadahiro Kuroda, Takeshi Fujita, S. Mita, +10

IEEE Journal of Solid-State Circuits

Low-power ElectronicsCore ProcessorElectrical EngineeringCo-processorsEngineering +13

50% active-power saving without speed degradation using standby power reduction (SPR) circuit

K. Seta, Hiroyuki Hara, Tadahiro Kuroda, +2

Standby Power ReductionVlsi DesignEngineeringEnergy EfficiencyActive Power Dissipation +16

Power-supply voltage impact on circuit performance for half and lower submicrometer CMOS LSI

M. Kakumu, M. Kinugawa

IEEE Transactions on Electron Devices

Low-power ElectronicsDevice ModelingElectrical EngineeringPower-supply Voltage ImpactExperimental Results +11

Hot-carrier generation in submicrometer VLSI environment

T. Sakurai, K. Nogami, M. Kakumu, +1

IEEE Journal of Solid-State Circuits

Device ModelingElectrical EngineeringEngineeringVlsi DesignVlsi Architecture +10

A high-speed low-power 0.3 μm CMOS gate array with variable threshold voltage (VT) scheme

Tadahiro Kuroda, Takeshi Fujita, T. Nagamatu, +8

Low-power ElectronicsHardware SecurityElectrical EngineeringHigh-speed Low-power 0.3Vlsi Design +11

Choice of power-supply voltage for half-micrometer and lower submicrometer CMOS devices

M. Kakumu, M. Kinugawa, Koh Hashimoto

IEEE Transactions on Electron Devices

Low-power ElectronicsElectrical EngineeringCmos DevicesEngineeringVlsi Design +12

Low-resistivity poly-metal gate electrode durable for high-temperature processing

Y. Akasaka, Sho Suehiro, K. Nakajima, +10

IEEE Transactions on Electron Devices

Materials ScienceMaterials EngineeringElectrical EngineeringConducting PolymerEngineering +13

Effects of silicon surface orientation on submicron CMOS devices

M. Kinugawa, M. Kakumu, T. Usami, +1

Electrical EngineeringEngineeringTriode Channel TransconductanceNanoelectronicsSilicon Surface Orientation +10

65 nm CMOS technology (CMOS5) with high density embedded memories for broadband microprocessor applications

N. Yanagiya, Shôichi Matsuda, S. Inaba, +31

EngineeringVlsi DesignComputer ArchitectureHigh DensityAdvanced Packaging (Semiconductors) +15

Electron paramagnetic resonance study on the annealing behavior of vacuum deposited amorphous silicon on crystalline silicon

Iwao Ohdomari, M. Kakumu, Hirohiko Sugahara, +4

Journal of Applied Physics

Electrical EngineeringCrystalline SiliconEngineeringIon ImplantationPhysics +12