Tomonori Sekiguchi - Concepedia

Author

Tomonori Sekiguchi

Hitachi (Japan)ORCID

Also Known As

Sekiguchi, Tomonori, T Sekiguchi, T. Sekiguchi, Tomonori - Sekiguchi, Tomonori SEKIGUCHI, Tomonori Sekiguchi

Publications

526

Citations

H-Index

Concepts

All Affiliations

Hitachi (Japan)

About

Tomonori Sekiguchi is an author at Hitachi (Japan) specializing in engineering, microelectronics, and computer engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	12	12	382
2	Computer Engineering	8	8	247
3	Electrical Engineering	8	8	245
4	Mechanical Engineering	3	3	98
5	Computer Science	1	1	36

Tomonori Sekiguchi

Publications

406

Citations

H-Index

Page 1

	Year	Citations
A 1-gb/s/pin 512-mb ddrii sdram using a digital dll and a slew-rate-controlled output buffer T. Matano, Y. Takai, T. Takahashi, IEEE Journal of Solid-State Circuits Slew-rate-controlled Output BufferEngineeringVlsi DesignAnalog-to-digital ConverterData Converter	2003	65
MEMS Gyroscope With Concentrated Springs Suspensions Demonstrating Single Digit Frequency Split and Temperature Robustness J. Giner, Daisuke Maeda, Kazuo Ono, Journal of Microelectromechanical Systems EngineeringX-y Symmetric ResonatorPhysicsMicrofabricationTemperature Robustness	2018	42
1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing Tomonori Sekiguchi, Kazuo Ono, Akira Kotabe, IEEE Journal of Solid-State Circuits EngineeringMemory DesignComputer ArchitectureData BusMulti-channel Memory Architecture	2011	41
Capacitive MEMS Accelerometer With Perforated and Electrically Separated Mass Structure for Low Noise and Low Power Y. Kamada, Atsushi Isobe, T. Oshima, Journal of Microelectromechanical Systems EngineeringMems ElementsMechanical EngineeringAccelerometerMicroelectromechanical Systems	2019	41
A 22-ng/$\surd$ Hz 17-mW Capacitive MEMS Accelerometer With Electrically Separated Mass Structure and Digital Noise- Reduction Techniques Yuki Furubayashi, T. Oshima, Taizo Yamawaki, IEEE Journal of Solid-State Circuits Electrical EngineeringBiomedical SensorsEngineeringSensorsMicrofabrication	2020	37
A 29-ns 64-Mb DRAM with hierarchical array architecture M. Nakamura, Tsuyoshi Takahashi, T. Akiba, IEEE Journal of Solid-State Circuits Hardware SecurityElectrical EngineeringMemory ArchitectureEngineeringVlsi Design	1996	36
A multigigabit DRAM technology with 6F/sup 2/ open-bitline cell, distributed overdriven sensing, and stacked-flash fuse Tsuyoshi Takahashi, Tomonori Sekiguchi, R. Takemura, IEEE Journal of Solid-State Circuits Non-volatile MemoryElectrical EngineeringChip-scale PackageEngineeringAdvanced Packaging (Semiconductors)	2001	31
An experimental 220 MHz 1 Gb DRAM Masashi Horiguchi, T. Sakata, Tomonori Sekiguchi, Electrical EngineeringEngineeringFlash MemoryMulti-channel Memory ArchitectureIn-memory Database	2002	29
Low-noise, high-speed data transmission using a ringing-canceling output buffer Tomonori Sekiguchi, Masashi Horiguchi, T. Sakata, IEEE Journal of Solid-State Circuits Ringing-canceling Output BufferEngineeringClock RecoveryData CommunicationMixed-signal Integrated Circuit	1995	16
An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture T. Sakata, Masashi Horiguchi, Tomonori Sekiguchi, IEEE Journal of Solid-State Circuits Electrical EngineeringMemory ArchitectureEngineeringVlsi DesignVlsi Architecture	1995	15

Page 1