A deep sub-V, single power-supply SRAM cell with multi-V/sub T/, boosted storage node and dynamic load

Abstract

The key issues in ultralow voltage SRAM design are a reduction in power supply voltage to a solar-cell voltage of 0.5V or less, single supply operation, and an increase in the cell voltage-margin. However, these problems remain largely unsolved. Even in most advanced cells an unavoidably high FET threshold voltage (V/sub T/) of the cell compared with the low stored node-voltage of supply restricts the supply to around 1V, although 0.5 V operation has been reported with no cell margin. Moreover, the negative pull down of the cell source line prevents single supply operation, since an on-chip negative voltage generator comprising charge pumping circuits never manages a heavy data-line capacitance. This paper describes an innovative circuit for overcoming these problems, demonstrating the feasibility of a single 0.3 V, 50 MHz, 0.25 /spl mu/m 8Kb SRAM. A multi-V/sub T/ cell, a boosted cell storage-node and a dynamic cell load contribute to the outstanding performance.