Area Overhead Analysis
Area Overhead Analysis is a methodological assessment within integrated circuit design that quantifies the additional physical layout area incurred by implementing clock gating structures relative to an ungated clocking scheme.
890
Publications
34.9K
Citations
2.4K
Authors
539
Institutions
Publications per year
2017–2026
152
Parents
890
William J. Dally, Brian Towles · 2001 · 3.2K citations
Engineering, Computer Engineering, Electrical Engineering +17
A Regular Layout for Parallel Adders
Brent, Kung · IEEE Transactions on Computers · 1982 · 1.1K citations
A distributed BIST control scheme for complex VLSI devices
Y. Zorian · 2002 · 543 citations
Engineering, Computer Engineering, Electrical Engineering +12
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Intel (United States)
Santa Clara, United States
20 h-index
69 publications
3.7K citations
National Tsing Hua University
Hsinchu, Taiwan
17 h-index
78 publications
6.2K citations
Politecnico di Torino
Turin, Italy
15 h-index
71 publications
2.3K citations
The University of Texas at Austin
Austin, United States
14 h-index
35 publications
1.8K citations
Universidade Federal do Rio Grande do Sul
Porto Alegre, Brazil
14 h-index
53 publications
2K citations
Stanford University
Stanford, United States
13 h-index
43 publications
8.4K citations

Centre National de la Recherche Scientifique
Paris, France
12 h-index
46 publications
1.3K citations
University of Southern California
Los Angeles, United States
12 h-index
31 publications
1.5K citations
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54 publications · 2K citations
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46 publications · 2K citations
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19 publications · 673 citations
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16 publications · 732 citations
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