Area Overhead Analysis

Area Overhead Analysis is a methodological assessment within integrated circuit design that quantifies the additional physical layout area incurred by implementing clock gating structures relative to an ungated clocking scheme.

890

Publications

34.9K

Citations

2.4K

Authors

539

Institutions

Publications per year

2017–2026

152

Authors

2.4K

  1. CW
    Cheng‐Wen Wu

    National Tsing Hua University, Taiwan

    14 publications · 672 citations

    12

    h-index

  2. NA
    Nur A. Touba

    The University of Texas at Austin, United States

    12 publications · 880 citations

    11

    h-index

  3. RK
    Ramesh Karri

    New York University, United States

    11 publications · 494 citations

    11

    h-index

  4. EM
    E.J. McCluskey

    Stanford University, United States

    10 publications · 596 citations

    10

    h-index

  5. CM
    Cecilia Metra

    University of Bologna, Italy

    10 publications · 250 citations

    10

    h-index

1–5 of 2.4K

Venues

  1. 26

    h-index

  2. 23

    h-index

  3. IEEE Transactions on Computers

    22 publications · 2.1K citations

    17

    h-index

  4. IEEE Journal of Solid-State Circuits

    19 publications · 673 citations

    15

    h-index

  5. 14

    h-index

1–5