Cache Memory Design is a systematic methodology within computer architecture that specifies the organization, mapping, replacement, and write policies of a high-speed memory subsystem to optimize data access latency and bandwidth efficiency relative to a processor's performance requirements.
515
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20K
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371
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Publications per year
2017–2026
63
Parents
Publications
515
James Laudon, Daniel Lenoski · 1997 · 779 citations · Full text
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
Guangyu Sun, Xiangyu Dong, Yuan Xie et al. · 2009 · 439 citations
Data speculation support for a chip multiprocessor
Lance Hammond, Mark Willey, Kunle Olukotun · 1998 · 420 citations
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371
Intel (United States)
Santa Clara, United States
18 h-index
146 publications
6.6K citations
IBM (United States)
Armonk, United States
17 h-index
113 publications
6.2K citations
Purdue University West Lafayette
West Lafayette, United States
16 h-index
76 publications
4.5K citations
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
12 h-index
32 publications
2.5K citations
University of California, Berkeley
Berkeley, United States
11 h-index
27 publications
1.2K citations
Stanford University
Stanford, United States
11 h-index
38 publications
2.8K citations
Toshiba (Japan)
Tokyo, Japan
11 h-index
123 publications
3.8K citations
Universitat Politècnica de Catalunya
Barcelona, Spain
11 h-index
27 publications
550 citations
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- IEEE Journal of Solid-State Circuits
29 publications · 1.8K citations
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- IEEE Micro
16 publications · 524 citations
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- IEEE Transactions on Computers
16 publications · 427 citations
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- ACM SIGARCH Computer Architecture News
12 publications · 487 citations
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- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
9 publications · 320 citations
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