A novel architecture of the 3D stacked MRAM L2 cache for CMPs

TLDR

MRAM offers fast read, high density, and non‑volatility, yet suffers from long write latency and high energy, and 3D stacking onto CMPs is now feasible and cost‑efficient. The study aims to evaluate MRAM‑based L2 caches stacked on CMPs versus SRAM, and to propose architectural solutions to mitigate write latency and energy. The authors implement direct MRAM stacking on CMPs, benchmark its performance and energy against SRAM, and introduce a read‑preemptive write buffer and an SRAM‑MRAM hybrid L2 cache to address write drawbacks. Direct MRAM stacking degrades performance because of long write latency and high energy, but the proposed hybrid design boosts performance by 4.91 % and cuts power by 73.5 % compared to a conventional SRAM L2 cache of similar area.

Abstract

Magnetic random access memory (MRAM) is a promising memory technology, which has fast read access, high density, and non-volatility. Using 3D heterogeneous integrations, it becomes feasible and cost-efficient to stack MRAM atop conventional chip multiprocessors (CMPs). However, one disadvantage of MRAM is its long write latency and its high write energy. In this paper, we first stack MRAM-based L2 caches directly atop CMPs and compare it against SRAM counterparts in terms of performance and energy. We observe that the direct MRAM stacking might harm the chip performance due to the aforementioned long write latency and high write energy. To solve this problem, we then propose two architectural techniques: read-preemptive write buffer and SRAM-MRAM hybrid L2 cache. The simulation result shows that our optimized MRAM L2 cache improves performance by 4.91% and reduces power by 73.5%compared to the conventional SRAM L2 cache with the similar area.