Titanium disilicide contact resistivity and its impact on 1-µm CMOS circuit performance

Abstract

A major feature of modern 1-µm CMOS technology is the use of TiSi <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> -clad diffusions with effective sheet resistances of typically 1 Ω /square. However, until now very little attention has been given to the contact resistance between the TiSi <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> and the underlying diffusions which form the source and drain of the active transistors. Our experimental results have shown that, depending on process conditions, the specific contact resistivity from silicide to n-diffusion varies by six orders of magnitude. In this work it is demonstrated that unless proper care is taken with respect to junction doping concentrations and post-silicide processing to minimize the silicide to diffusion contact resistance, the use of silicided diffusions actually can be detrimental to circuit performance instead of the intended performance enhancement. In this paper we will present: 1) a novel method to evaluate silicide to diffusion contact resistance using only two masks, 2) an outline of the process conditions that yield a minimum contact resistance, 3)circuit simulations showing the impact of this work on circuit performance, and 4) results showing that the modulation of the contact resistance at high current levels can distort the MOS linear region current-voltage characteristics.