2008 · 38 citations · 3 references
EngineeringMaterials EngineeringMaterials ScienceElectronic MaterialsInterface ScienceSemiconductor DevicesChip PackagingIntegrated Circuit DesignMetallic BondingSemiconductor InterfacesWafer BondingAtmospheric PressureBondingDirect Wafer BondingLow-temperature BondingSiliconThree-dimensional Integration
In 3D integration circuits, metal bonding is a key stage for stacking wafers. In this contribution, the direct Cu/Cu bonding at atmospheric pressure is investigated. At room temperature, a 2.8 J/m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> bonding toughness is achieved without copper oxide at the interface. The vertical current of this bonding and the possibility to grind the top silicon down to 10 μm have been demonstrated.
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Bonding of silicon wafers for silicon-on-insulator
W. Maszara, Georges Goetz, A.L. Caviglia et al. · Journal of Applied Physics · 1988 · 861 citations
Enabling technologies for 3D chip stacking
Patrick Leduc, L. Di Cioccio, Barbara Charlet et al. · 2008 · 48 citations