IEEE Electron Device Letters · 1992 · 34 citations · 8 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureMicroelectronicsSemiconductor DevicesDevice ModelingDevice SimulationMemory ModelingMemory Subsystem DesignErase CyclingFixed Oxide ChargeMemory Wear ModelingNon-volatile Memory DesignOxide ChargeProgram CyclingThreshold VoltageVolatile Memory Modeling
A theoretical model that explains the programming window degradation and the corresponding high- and low-state threshold voltage shifts as a function of the number of write-erase operations in FLOTOX EEPROM cells is proposed. The collapse of the programming window is quantitatively related to the oxide charge buildup in the FLOTOX tunnel region as the cycling of the memory cell is increased. The simplicity of the model should make possible a direct application at CAD level.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Analysis and modeling of floating-gate EEPROM cells
Avinoam Kolodny, S. T. K. Nieh, B. Eitan et al. · IEEE Transactions on Electron Devices · 1986 · 178 citations