Erase Cycling
Erase Cycling is a fundamental wear mechanism in solid-state storage characterized by the repeated process of erasing data from a block of non-volatile memory cells, which progressively degrades the oxide layers within the cells and limits the block's usable lifespan.
125
Publications
5.1K
Citations
576
Authors
140
Institutions
Publications per year
2017–2026
13
Parents
125
Bit error rate in NAND Flash memories
Neal Mielke, Todd A. Marquart, Ning Wu et al. · 2008 · 358 citations
Read Disturb Errors in MLC NAND Flash Memory: Characterization, Mitigation, and Recovery
Yu Cai, Yixin Luo, Saugata Ghose et al. · 2015 · 204 citations · Full text
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140
IMEC
Leuven, Belgium
10 h-index
51 publications
1.4K citations
Intel (United States)
Santa Clara, United States
9 h-index
41 publications
5.6K citations
Korea Advanced Institute of Science and Technology
Daejeon, South Korea
6 h-index
16 publications
221 citations
Samsung (South Korea)
Seoul, South Korea
5 h-index
17 publications
257 citations
IBM Research - Zurich
Rüschlikon, Switzerland
3 h-index
13 publications
410 citations
Politecnico di Milano
Milan, Italy
3 h-index
13 publications
265 citations
Hitachi (Japan)
Tokyo, Japan
3 h-index
9 publications
345 citations
STMicroelectronics (Italy)
Milan, Italy
3 h-index
6 publications
162 citations
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12 publications · 320 citations
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14 publications · 347 citations
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10 publications · 724 citations
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JJAP · 7 publications · 197 citations
7
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3 publications · 200 citations
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