2007 · 60 citations · 2 references
EngineeringElectrical EngineeringMicroelectronicsMicrofabricationSemiconductor DevicesChip PackagingIntegrated Circuit DesignIntegrated Circuit DevicesIntegrated Circuit FabricationInterconnect TechnologyWafer Bonding3D Integrated CircuitsAdvanced PackagingInterconnect FabricationMultilevel InterconnectsThree-dimensional Integrated Circuit InterconnectsThree-dimensional Integrated Circuit LayoutThree-dimensional IntegrationThrough-silicon Vias
Three dimensional stacked circuits having multiple active semiconductor levels rely on the development of strata bonding, micro connects between strata, through strata vias (TSV) and a wafer thinning process. Progress in the each of these process technologies for 3D strata stacking is opening the path to more robust and capable 3D process integrations.
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