IEEE Transactions on Device and Materials Reliability · 2004 · 117 citations · 18 references
Non-volatile MemoryFlash Memory CellsEngineeringTunnel OxideComputer ArchitectureInterface Trap GenerationChannel WidthTunneling MicroscopyNanoelectronicsMemory DeviceMemory DevicesElectrical EngineeringPhysicsBias Temperature InstabilityFlash MemoryComputer EngineeringMicroelectronicsMemory ReliabilityStress-induced Leakage CurrentApplied PhysicsSemiconductor MemoryData Retention CharacteristicsSlow TrapsElectrical Insulation
It is revealed that the interface trap generation rate increases by Fowler-Nordheim current stressing on the tunnel oxide as the channel width of shallow-trench isolation (STI)-isolated NAND flash cells shrinks. Furthermore, we argue that the interface trap annihilation phenomenon during retention mode becomes a major failure mechanism of the data retention characteristics of sub-100-nm cells in addition to the conventional charge loss mechanism. A new interface trap analysis method using the hysteresis of the I/sub d/--V/sub g/ curve is proposed and shows that the interface traps consist of fast traps and slow traps.
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