Trends for deep submicron VLSI and their implications for reliability

Abstract

We examine the technology trends in both device and interconnect process integration flow design, in order to put into perspective the corresponding implications on reliability activities. We illustrate trends in several major reliability areas: reduced failure rate requirements; vanishing of excess reliability margins; sensitivity of reliability mechanisms integration flow design and scaling; increased use of simulation to estimate reliability; and examining mechanisms for new regimes of operation. Next we assess the strengths and weaknesses of current build-in reliability activities. This process identifies several key areas where improved knowledge and capability are needed in the overall build-in reliability process: improve the circuit modeling of wearout phenomena; develop new gate dielectrics to increase performance while maintaining reliability; determine if there is a discontinuity caused by entering the direct tunneling regime of gate oxide operation; increase understanding of thermal limitations on interconnect design guidelines in multilevel metal systems; and enhance emerging methodologies for ESD/EOS build-in reliability.