Electrical measurement of feature sizes in MOS Si²-gate VLSI technology

Abstract

The reduced device dimensions of VLSI circuits resulting from improved lithographic techniques require very careful control of the feature sizes during the production process. For this purpose, test patterns and measurement techniques for automatic electrical measurements of misalignments and feature sizes have been developed for the control of an MOS Si <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> -gate process. Using these methods, correlations between the electrically relevant device parameters and the feature sizes are obtained. A sensitivity analysis for the threshold voltage has been made. It was found that for the technology under consideration, the variation of the feature sizes predominates over the influences of all other technological parameters at transistor lengths of 1-2 µm.