IEEE Journal of Solid-State Circuits · 1986 · 31 citations · 9 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignDevice ReliabilityMemory DevicesMemory Hierarchy DesignMemory Subsystem DesignShort-channel EffectsDynamic Random-access MemoryDynamic Random-access Memory DesignMemory Circuit DesignNon-volatile Memory Design
An experimental 5-V-only 1M-word/spl times/4-bit dynamic RAM with page and SCD modes has been built in a relatively conservative 1-/spl mu/m CMOS technology with double-level metal and deep trenches. It uses a cross-point one-transistor trench-transistor cell that measures only 9 /spl mu/m/SUP 2/. A double-ended adaptive folded bit-line architecture used on this DRAM provides the breakthrough needed to take full density advantage of this cross-point cell. The 30-fF storage capacitance of this cell is expected to provide high alpha immunity since the charge is stored in polysilicon and is oxide isolated from the substrate. A 150-ns now-address-stable access time and 40-ns column-address-strobe access time have been observed.
9
A corrugated capacitor cell (CCC) for megabit dynamic MOS memories
H. Sunami, T. Kure, N. Hashimoto et al. · 1982 · 57 citations
Engineering, Computer Engineering, Electrical Engineering +15
A trench transistor cross-point DRAM cell
W.F. Richardson, D.M. Bordelon, G. Pollack et al. · 1985 · 47 citations
An isolation-merged vertical capacitor cell for large capacity DRAM
Satoshi Nakajima, Kouichi Miura, K. Minegishi et al. · 1984 · 26 citations
A 4Mb DRAM with cross point trench transistor cell
A.H. Shah, C. Wang, R.H. Womack et al. · 1986 · 25 citations
Engineering, Computer Engineering, Electrical Engineering +13