1986 · 25 citations · 3 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyIntegrated Circuit DesignMemory DevicesMemory Subsystem DesignMetal-oxide-semiconductor Field-effect TransistorsLeakage Current ReductionMemory Cell DesignMemory Circuit DesignStatic Random-access Memory Design
This report will describe the design of a 9.8mm×10.2mm 1MW×4b DRAM fabricated in a 1μm double-level metal CMOS technology featuring trench-transistor cells measuring 9μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Row and static column access times are 170ns and 30ns, respectively.
3
A trench transistor cross-point DRAM cell
W.F. Richardson, D.M. Bordelon, G. Pollack et al. · 1985 · 47 citations
A 1Mb CMOS DRAM with design-for-test functions
Joseph Neal, Brian Holland, Satoshi Inoue et al. · 1986 · 13 citations
Engineering, Computer Engineering, Electrical Engineering +12