An isolation-merged vertical capacitor cell for large capacity DRAM

Abstract

An isolation-merged vertical capacitor (IVEC) cell is described with emphasis on its scalability, simulated device characteristics and experimentally obtained capacitor oxide breakdown voltage. The IVEC cell size will be reduced to around 5 µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> by using the 0.5 µm rule process and trench depth of 2.2 µm. Capacitor oxide breakdown voltage is nearly the same with the conventional trench capacitor.