Evaluation and optimization of die-shift in Embedded Wafer-Level Packaging by enhancing the adhesion strength of silicon chips to carrier wafer

Abstract

In this paper, we focus on a method to evaluate and to optimize the die shift that occurs during epoxy molding for embedded wafer level technology (eWLB), basically by adjusting the adhesion level of silicon dies on top of the temporary carrier support. Here, a stress-free 70μm thick silicon dies were prepared using dicing before grinding process (DBG). Then a total of 495 dies were placed on a 8inch silicon carrier wafer that it was preliminary coated with two different adhesive layers made by pressure sensitive laminate and by a thermoplastic like spin-coated films. A 5μm thick copper marks have been manufactured by through resist electroplating process on the carrier wafer prior to the adhesive coating, and on each dies prior to the DBG process. Those copper marks were then used to evaluate the die shift after epoxy molding using X-ray microscopy and image processing software. The adhesion strength of silicon dies were studied through die shear measurement, and the pick and place process parameters were subsequently adjusted to obtain the utmost adhesion level. An optimal die shift of 30μm ± 15μm has been achieved after epoxy molding process for an optimal applied pressure and an optimal temperature-pressure parameters for pressure sensitive and thermoplastic layers, respectively.