Vasarla Nagendra Sekhar

Fabrication of High Aspect Ratio TSV and Assembly With Fine-Pitch Low-Cost Solder Microbump for Si Interposer Technology With High-Density Interconnects

Aibin Yu, John H. Lau, Soon Wee Ho et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 2011 · 65 citations

Engineering, Integrated Circuits, Interconnect (Integrated Circuits) +20

Wafer level embedding technology for 3D wafer level embedded package

Aditya Kumar, Xia Dingwei, Vasarla Nagendra Sekhar et al. · 2009 · 49 citations

Engineering, Mechanical Engineering, Computer Architecture +18

Low-Loss Broadband Package Platform With Surface Passivation and TSV for Wafer-Level Packaging of RF-MEMS Devices

Bangtao Chen, Vasarla Nagendra Sekhar, Jin Cheng et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 2013 · 47 citations

Engineering, Radio Frequency, Wafer-level Packaging +19

Embedded wafer level packages with laterally placed and vertically stacked thin dies

Gaurav Sharma, Vempati Srinivas Rao, Aditya Kumar et al. · 2009 · 34 citations

Engineering, Mechanical Engineering, Interconnect (Integrated Circuits) +18

Antenna-in-Package Design Based on Wafer-Level Packaging With Through Silicon Via Technology

Jin Cheng, Vasarla Nagendra Sekhar, Xiaoyue Bao et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 2013 · 32 citations

Engineering, Radio Frequency, Wafer-level Packaging +19