IEEE Journal of Solid-State Circuits · 1986 · 28 citations · 14 references
EngineeringComputer EngineeringElectrical EngineeringMemoryMicroelectronicsSemiconductor DevicesCmos Circuit DesignDevice ReliabilityIntegrated Circuit DesignMemory DevicesSemiconductor ReliabilityShort-channel EffectsBondingCmos ReliabilityCycle TimeDynamic Random-access Memory DesignMemory Array ArchitectureMemory Circuit DesignNon-volatile Memory DesignOn-chip Memory Design
A 4-Mb dynamic RAM has been designed and fabricated using 1.0-/spl mu/m twin-tub CMOS technology. The memory array consists of trenched n-channel depletion-type capacitor cells in a p-well. Very high /spl alpha/-particle immunity was achieved with this structure. One cell measures 3.0/spl times/5.8 /spl mu/m/SUP 2/ yielding a chip size of 7.84/spl times/17.48 mm/SUP 2/. An on-chip voltage converter circuit was implemented as a mask option to investigate a possible solution to the MOSFET reliability problem caused by hot carriers. An 8-bit parallel test mode was introduced to reduce the RAM test time. Metal mask options provide static-column-mode and fast-age-mode operation. The chip is usable as /spl times/1 or /spl times/4 organizations with a bonding option. Using an external 5-V power supply, the row-address-strobe access time is 80 ns at room temperature. The typical active current is 60 mA at a 220-ns cycle time with a standby current of 0.5 mA.
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A New Physical Mechanism for Soft Errors in Dynamic Memories
T.C. May, M. H. Woods · Reliability physics · 1978 · 228 citations
An experimental 1Mb DRAM with on-chip voltage limiter
K. Itoh, R. Hori, J. Etoh et al. · 1984 · 66 citations
Engineering, Computer Engineering, Electrical Engineering +15
A corrugated capacitor cell (CCC) for megabit dynamic MOS memories
H. Sunami, T. Kure, N. Hashimoto et al. · IEEE Electron Device Letters · 1983 · 39 citations
Engineering, Computer Engineering, Electrical Engineering +15