Takashi Ohsawa

Memory design using a one-transistor gain cell on SOI

Takashi Ohsawa, K. Fujita, Tatsuya Higashi et al. · IEEE Journal of Solid-State Circuits · 2002 · 96 citations

Non-volatile Memory, Electrical Engineering, Engineering +9

A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme

Takashi Ohsawa, Hiroki Koike, S. Miura et al. · IEEE Journal of Solid-State Circuits · 2013 · 81 citations

Non-volatile Memory, Engineering, Memory Design +17

High-speed simulator including accurate MTJ models for spintronics integrated circuit design

Noboru Sakimura, Ryusuke Nebashi, Y. Tsuji et al. · 2012 · 60 citations

Engineering, Vlsi Design, Computer Architecture +19

1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times

Takashi Ohsawa, Hiroki Koike, S. Miura et al. · 2012 · 59 citations

Non-volatile Memory, Engineering, Memory Design +17

A 1.5nsec/2.1nsec random read/write cycle 1Mb STT-RAM using 6T2MTJ cell with background write for nonvolatile e-memories

Takashi Ohsawa, S. Miura, Kentaro Kinoshita et al. · 2013 · 34 citations

Non-volatile Memory, Electrical Engineering, Engineering +11