Memory design using a one-transistor gain cell on SOI

Abstract

A 512-kb memory has been developed featuring a one-transistor gain cell of size 7F/sup 2/ (F = 0.18 /spl mu/m) on SOI. The cell named the floating body transistor cell (FBC) has the ability to achieve a 4F/sup 2/ cell using self-aligned contact technologies and is proved to be scalable with respect to a cell signal. A basic operation was verified by device simulation and hardware measurement. An array driving method is disclosed which makes selective write possible. A cell signal sensing system consisting of a pair of reference cells written opposite data and comparing the combined current with the doubled cell current is shown to be robust against cell parameter variations in process and temperature. A random access time of 40 ns was simulated. Nondestructive readout and C/sub b//C/sub s/. free signal development drastically improve cell efficiency.