EngineeringComputer EngineeringElectrical EngineeringMemoryMicroelectronicsSemiconductor DevicesDevice CharacterizationDevice ModelingDynamic Power ReductionMemory Subsystem DesignPower ManagementCycle TimeEnergy-efficient Memory DesignLeakage Current ModelingMemory Power ManagementMemory Power OptimizationPower-efficient Memory DesignVoltage Scaling In Memory Systems
This paper will report on an experimental 21μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> cell, single 5V 1Mb NMOS DRAM. Typical clata are: access time 90ns, power dissipation 300mW at 260ns cycle time. Chip area is 46mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
2
A corrugated capacitor cell (CCC) for megabit dynamic MOS memories
H. Sunami, T. Kure, N. Hashimoto et al. · 1982 · 57 citations
Engineering, Computer Engineering, Electrical Engineering +15
Submicron VLSI memory circuits
T. Mano, J. Yamada, Junpei Inoue et al. · 1983 · 27 citations
Engineering, Computer Engineering, Electrical Engineering +11