An experimental 1Mb DRAM with on-chip voltage limiter

Abstract

This paper will report on an experimental 21μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> cell, single 5V 1Mb NMOS DRAM. Typical clata are: access time 90ns, power dissipation 300mW at 260ns cycle time. Chip area is 46mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>