H. Ishiuchi

Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length

K. Okano, T. Izumida, H. Kawasaki et al. · 2006 · 76 citations

Engineering, Electrical Engineering, Microfabrication +16

High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

S. Inaba, K. Okano, Shôichi Matsuda et al. · IEEE Transactions on Electron Devices · 2002 · 75 citations

Engineering, Electrical Engineering, Microelectronics +16

High-Performance FinFET with Dopant-Segregated Schottky Source/Drain

A. Kaneko, A. Yagishita, K. Yahashi et al. · 2006 · 53 citations

Engineering, Electrical Engineering, Electronic Materials +11

Ultrathin gate oxide CMOS on [111] surface-oriented Si substrate

H.S. Momose, T. Ohguro, Shigenari Nakamura et al. · IEEE Transactions on Electron Devices · 2002 · 52 citations

Engineering, Electrical Engineering, Materials Science +17

MOSFET design for forward body biasing scheme

A. Hokazono, Sriram Balasubramanian, K. Ishimaru et al. · IEEE Electron Device Letters · 2006 · 45 citations

Engineering, Electrical Engineering, Microelectronics +16