A damage-free perfect planarization method using bias-sputtered SiO₂

Abstract

A novel bias-sputtered SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> deposition process, which is suitable for depositing an interlevel insulator of an Al multilevel interconnection of submicrometer feature size, has been achieved. This process consists of damage-free technology and a perfect planarization method. It was found that during the bias-sputter deposition, damage was introduced into the gate oxides of MOS devices due to secondary X-rays generated by electrons coming from the sputter target, but that the presence of a grid electrode to absorb these electrons was quite effective to reduce damage introduction to an acceptable degree for practical use. Also, using a two-step bias-sputter deposition and an etch-back technique, a perfect planarization of bias-sputtered SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> films was achieved.