A VLSI Bipolar Metallization Design with Three-Level Wiring and Area Array Solder Connections

Abstract

The ability to interconnect large numbers of integrated silicon devices on a single chip has been greatly aided by a three-level wiring capability and large numbers of solderable input/output terminals on the face of the chip. This paper describes the design and process used to fabricate the interconnections on IBM's most advanced bipolar devices. Among the subjects discussed are thin film metallurgy and contacts, e-beam lithography and associated resist technology, a high temperature lift-off stencil for metal pattern definition, planarized rf sputtered SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> insulation/passivation, the “zero-overlap” via hole innovation, in situ rf sputter cleaning of vias prior to metallization, and area array solder terminals.