Experimental Study of Gate-First FinFET Threshold-Voltage Mismatch

Abstract

In this brief, threshold voltage mismatch of fully integrated n-type FinFETs based on a gate-first process was studied experimentally. Significantly improved threshold voltage mismatch due to undoped FIN body was confirmed with the experimental data. By comparing mismatch values of thin- and thick-oxide nMOS, we found that factors, which do not scale with gate oxide thickness, including line edge roughness and metal-gate granularity (MGG), can explain ~ 60% of total mismatch of thin-oxide devices. Moreover, we report a convex shape of threshold voltage mismatch following the increase of the number of FINs and propose a possible explanation of the abnormal behavior. Due to channel width quantization, two competing contributors impact mismatch: as FIN number becomes smaller mismatch due to MGG likely play an important role which increases threshold voltage mismatch, whereas FIN number becomes larger, systematic variation becomes the main factor, which also increases threshold voltage mismatch.