71 mV/dec of sub-threshold slope in vertical tunnel field-effect transistors with GaAsSb/InGaAs heterostructure

Motohiko Fujimatsu, Hisashi Saito, Yasuyuki Miyamoto

2012 · 17 citations · 7 references

Concepts

Abstract

We fabricated a vertical tunnel field-effect transistor (TFET) with a GaAsSb/InGaAs heterojunction using a 5-nm-thick Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> dielectric. The 26-nm width of the narrow channel mesa structure was confirmed using citric acid solution. The minimum sub-threshold slope (SS) was 71 mV/dec. On the basis of our simulated and experimental results, the SS was estimated to be 54 mV/dec for an effective oxide thickness (EOT) of 1 nm.

References

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