PolySi-SiO[sub 2]-ZrO[sub 2]-SiO[sub 2]-Si Flash Memory Incorporating a Sol-Gel-Derived ZrO[sub 2] Charge Trapping Layer

Abstract

In this paper, we propose a method for depositing the charge trapping layer of a high- (SOZOS) memory device. In this approach, the trapping layer was formed through simple two steps: (i) spin-coating of the precursor and (ii) rapid thermal annealing for at under an oxygen atmosphere. The morphology of the charge trapping layer was confirmed through X-ray photoemission spectroscopy analysis. The sol-gel-derived layer exhibited improved charge trapping in the SOZOS memory device, resulting in a threshold voltage shift of in the curve, (program/erase) speeds as fast as , good data retention up to (only a 5% charge loss due to deep trapping in the layer), and good endurance (no memory window narrowing after cycles).