Charge Trapping

Charge Trapping is a physical phenomenon in semiconductor devices whereby charge carriers are captured and immobilized at localized defect states within the gate dielectric or at the interface of a MOS capacitor, altering the threshold voltage and reliability characteristics in memory devices.

2.9K

Publications

145.7K

Citations

10.7K

Authors

1.6K

Institutions

Publications per year

2017–2026

624

Authors

10.7K

  1. DM
    Daniel M. Fleetwood

    Vanderbilt University, United States

    41 publications · 2.8K citations

    28

    h-index

  2. GG
    G. Groeseneken

    IMEC, Belgium

    50 publications · 1.8K citations

    26

    h-index

  3. DJ
    D. J. DiMaria

    IBM Research - Thomas J. Watson Research Center, United States

    26 publications · 2K citations

    22

    h-index

  4. RD
    R. Degraeve

    IMEC, Belgium

    31 publications · 1.1K citations

    21

    h-index

  5. RD
    Ronald D. Schrimpf

    Vanderbilt University, United States

    27 publications · 1.3K citations

    21

    h-index

1–5 of 10.7K

Venues

  1. Journal of Applied Physics

    278 publications · 15.9K citations

    68

    h-index

  2. Applied Physics Letters

    325 publications · 17.2K citations

    68

    h-index

  3. IEEE Transactions on Electron Devices

    263 publications · 13.4K citations

    57

    h-index

  4. IEEE Electron Device Letters

    185 publications · 7.6K citations

    47

    h-index

  5. IEEE Transactions on Nuclear Science

    118 publications · 6.9K citations

    44

    h-index

1–5