Multi-Stack Flip Chip 3D Packaging with Copper Plated Through-Silicon Vertical Interconnection

Abstract

3D packaging (3DP) is an emerging trend as a solution for microelectronics development toward system in package (SiP). 3D flip chip stacking structures with through silicon vias (TSVs) have very good potential for the implementation of 3D packaging. In this study, a prototype of multistack flip chip 3D packaging with TSVs for interconnection is designed and fabricated. Processing techniques for prototype fabrication are studied and discussed in details. The formation of TSVs is by the deep reactive ion etching (DRIE) process and the plugging of TSVs is by copper plating. Lead-free soldering and wafer thinning are also implemented in this prototype. In addition to the conceptual design, all wafer level fabrication processes are described and the subsequent die stacking assembly is also presented in this paper.