IC stacking technology using fine pitch, nanoscale through silicon vias - Concepedia

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IC stacking technology using fine pitch, nanoscale through silicon vias

32

Citations

2

References

2004

Year

S. Spiesshoefer, L.W. Schaper

Unknown Venue

3D Ic ArchitectureWafer Scale ProcessingEngineeringAdvanced Packaging (Semiconductors)MicrofabricationNanoelectronicsNanotechnologyApplied PhysicsFine PitchSemiconductor Device FabricationElectronic PackagingSilicon On InsulatorMicroelectronics

References

	Year	Citations

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