2005 · 26 citations · 9 references
EngineeringComputer EngineeringElectrical EngineeringFault-tolerant ComputingMicroelectronicsSemiconductor DevicesBuilt-in Self-testDelay ModelingDesign For TestabilityDevice ReliabilityTiming AnalysisTiming ModelingCircuit Delay ModelingDelay Fault TestingDelay SimulationPath Delay ModelingTiming Faults
A new delay testing scheme that identifies abnormal delays in the slack interval by comparing switching delays in neighboring dies on a wafer has been recently proposed and validated on experimental circuits. We evaluate the effectiveness of this new approach through the simulation of injected delay faults in the ISCAS benchmark circuits. The simulations are performed using a simple switched RC (resistor-capacitor) switching delay model. The results indicate that the new delay testing approach is orders of magnitude more effective in detecting and diagnosing smaller delay defects that increase circuit path delays by 10-50%. The new methodology can address increasing concerns that failure to detect such small delay faults during test may be the cause of significant unreliability in emerging nanometer technologies.
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A case study of ir-drop in structured at-speed testing
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