Metal Gate Scaling

Metal Gate Scaling is a semiconductor device scaling technique that specifically addresses the dimensional and material optimization of the metal gate electrode in transistor architectures to enhance electrostatic control and mitigate short-channel effects as feature sizes are reduced.

213

Publications

8.1K

Citations

Authors

167

Institutions

Publications per year

2017–2026

Parents

Device Scaling

Publications

213

High-K materials and metal gates for CMOS applications

John Robertson, Robert M. Wallace · Materials Science and Engineering R Reports · 2014 · 766 citations · Full text

Engineering, Electrical Engineering, Materials Science +16

A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications

C.-H. Jan, Uma Bhattacharya, R. Brain et al. · 2012 · 305 citations

Engineering, Computer Engineering, Electrical Engineering +16

45nm High-k + metal gate strain-enhanced transistors

C. Auth, A. Cappellani, Jang‐Soo Chun et al. · 2008 · 204 citations

Engineering, Computer Engineering, Electrical Engineering +17

Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

Hans Mertens, R. Ritzenthaler, Andriy Hikavyy et al. · 2016 · 198 citations

Engineering, Electrical Engineering, Materials Science +17

A 32nm logic technology featuring 2<sup>nd</sup>-generation high-k + metal-gate transistors, enhanced channel strain and 0.171&#x03BC;m<sup>2</sup> SRAM cell size in a 291Mb array

S. Natarajan, M Armstrong, M. Bost et al. · 2008 · 184 citations

Engineering, Computer Engineering, Electrical Engineering +16

1–5 of 213

Authors

VN
Vijay Narayanan
IBM (United States), United States
16 publications · 393 citations
13
h-index
EC
E. Cartier
IBM Research - Thomas J. Watson Research Center, United States
12 publications · 350 citations
11
h-index
SD
S. Deleonibus
Commissariat à l'Énergie Atomique et aux Énergies Alternatives, France
9 publications · 372 citations
9
h-index
TA
Takashi Ando
The University of Osaka, Japan
9 publications · 222 citations
9
h-index
MC
M. Chudzik
IBM (United States), United States
9 publications · 264 citations
9
h-index

1–5 of 2K

Institutions

167

1–8 of 167

Venues

IEEE Electron Device Letters
19 publications · 913 citations
14
h-index
IEEE Transactions on Electron Devices
12 publications · 435 citations
12
h-index
Microelectronic Engineering
12 publications · 297 citations
11
h-index
Silicon
2 publications · 38 citations
3
h-index
Symposium on VLSI Technology
Conference · 3 publications · 72 citations
3
h-index

1–5