S. Deleonibus

Impact of SOI, Si<inf>1-x</inf>Ge<inf>x</inf>OI and GeOI substrates on CMOS compatible Tunnel FET performance

F. Mayer, C. Le Royer, J.-F. Damlencourt et al. · 2008 · 237 citations

Semiconductor Technology, Electrical Engineering, Engineering +12

High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding

O. Weber, O. Faynot, F. Andrieu et al. · 2008 · 159 citations

Device Modeling, Semiconductor Technology, Electrical Engineering +14

Advances, challenges and opportunities in 3D CMOS sequential integration

P. Batude, M. Vinet, B. Prévitali et al. · 2011 · 148 citations · Full text

Materials Science, 3D Ic Architecture, Wafer Scale Processing +15

Lateral interband tunneling transistor in silicon-on-insulator

C. Aydin, A. Zaslavsky, Serge Luryi et al. · Applied Physics Letters · 2004 · 142 citations

Electrical Engineering, Engineering, Physics +9

Multiple gate devices: advantages and challenges

T. Poiroux, M. Vinet, O. Faynot et al. · Microelectronic Engineering · 2005 · 130 citations

Electrical Engineering, Engineering, Device Integration +4