S. Deleonibus - Concepedia

Author

S. Deleonibus

Commissariat à l'Énergie Atomique et aux Énergies Alternatives ORCID

Also Known As

Deleonibus, S., S Deleonibus, S. DELEONIBUS, S. Deleonibus, S. Deleonibus., Simon DELEONIBUS, Simon Deleonibus

373

Publications

Citations

H-Index

Concepts

All Affiliations

Commissariat à l'Énergie Atomique et aux Énergies Alternatives CEA Grenoble Laboratoire d'Électronique des Technologies de l'Information Institut polytechnique de Grenoble Université Grenoble Alpes

About

S. Deleonibus is an author at Commissariat à l'Énergie Atomique et aux Énergies Alternatives specializing in engineering, applied physics, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	34	114	4.4K
2	Applied Physics	34	103	3.9K
3	Natural Sciences	2	2	27
4	Chemical Engineering	2	2	23
5	Education	1	1	51

S. Deleonibus

121

Publications

4.5K

Citations

H-Index

Page 1

	Year	Citations
Impact of SOI, Si<inf>1-x</inf>Ge<inf>x</inf>OI and GeOI substrates on CMOS compatible Tunnel FET performance F. Mayer, C. Le Royer, J.-F. Damlencourt, Semiconductor TechnologyElectrical EngineeringEngineeringPhysicsApplied Physics	2008	237
High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding O. Weber, O. Faynot, F. Andrieu, Device ModelingSemiconductor TechnologyElectrical EngineeringEngineeringPhysics	2008	159
Advances, challenges and opportunities in 3D CMOS sequential integration P. Batude, M. Vinet, B. Prévitali, Materials Science3D Ic ArchitectureWafer Scale ProcessingEngineeringVlsi Design	2011	148
Lateral interband tunneling transistor in silicon-on-insulator C. Aydin, A. Zaslavsky, Serge Luryi, Applied Physics Letters Electrical EngineeringEngineeringPhysicsNanoelectronicsLateral Interband	2004	142
Multiple gate devices: advantages and challenges T. Poiroux, M. Vinet, O. Faynot, Microelectronic Engineering Electrical EngineeringEngineeringDevice IntegrationNanoelectronicsMultiple Gate Devices	2005	130
FDSOI devices with thin BOX and ground plane integration for 32nm node and below C. Fenouillet-Béranger, S. Denorme, P. Perreau, Solid-State Electronics 3D Ic ArchitectureElectrical EngineeringEngineeringVlsi DesignThin Box	2009	130
Bonded planar double-metal-gate NMOS transistors down to 10 nm M. Vinet, T. Poiroux, J. Widiez, IEEE Electron Device Letters Alignment MarksElectrical EngineeringEngineeringNanoelectronicsScaling Rules	2005	128
Advances in 3D CMOS sequential integration P. Batude, M. Vinet, A. Pouydebasque, EngineeringVlsi DesignSequential Cmos IntegrationSilicon On InsulatorCmos Sequential Integration	2009	114
15nm-diameter 3D stacked nanowires with independent gates operation: &#x03A6;FET C. Dupré, A. Hubert, Stéphane Bécu, Co-processed FinfetEngineeringIntegrated CircuitsIndependent-gate FinfetSemiconductor Device	2008	111
Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond O. Faynot, F. Andrieu, O. Weber, EngineeringVlsi DesignComputer ArchitectureIntegrated CircuitsNon Planar Devices	2010	104

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