Latchup Mitigation
Latchup Mitigation is a radiation hardening technique that prevents or suppresses the occurrence of parasitic conduction paths in integrated circuits caused by ionizing radiation, thereby maintaining device functionality and reliability.
220
Publications
6.3K
Citations
755
Authors
193
Institutions
Publications per year
2017–2026
14
Parents
220
Latch-Up in CMOS Integrated Circuits
B. L. Gregory, B.D. Shafer · IEEE Transactions on Nuclear Science · 1973 · 117 citations
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National Yang Ming Chiao Tung University
Hsinchu, Taiwan
15 h-index
41 publications
1.3K citations

Vanderbilt University
Nashville, United States
13 h-index
71 publications
3.1K citations
IBM (United States)
Armonk, United States
13 h-index
59 publications
1.4K citations
Texas Instruments (United States)
Dallas, United States
9 h-index
21 publications
498 citations
Sandia National Laboratories
Albuquerque, United States
9 h-index
26 publications
992 citations
Goddard Space Flight Center
Greenbelt, United States
8 h-index
21 publications
578 citations
Infineon Technologies (Germany)
Munich, Germany
7 h-index
22 publications
457 citations

Centre National d'Études Spatiales
Paris, France
7 h-index
13 publications
372 citations
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47 publications · 1.8K citations
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41 publications · 1K citations
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10 publications · 257 citations
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9 publications · 496 citations
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8 publications · 305 citations
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