Kevin Winstel

3D copper TSV integration, testing and reliability

Mukta Farooq, Troy Graves-Abe, W. Landers et al. · 2011 · 107 citations

Engineering, Electrical Engineering, Materials Science +17

Integration of trench DRAM into a high-performance 0.18 μm logic technology with copper BEOL

S. Crowder, R. Hannon, H. Ho et al. · 2002 · 23 citations

Engineering, Computer Engineering, Electrical Engineering +16

Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology

Pooja Batra, Spyridon Skordas, D. LaTulipe et al. · Journal of Low Power Electronics and Applications · 2014 · 19 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +17

Low temperature direct wafer to wafer bonding for 3D integration: Direct bonding, surface preparation, wafer-to-wafer alignment

G. Gaudin, G. Riou, Didier Landru et al. · 2010 · 17 citations

Engineering, Materials Engineering, Materials Science +15

Bonding technologies for chip level and wafer level 3D integration

Katsuyuki Sakuma, Spyridon Skordas, Jeffrey A. Zitz et al. · 2014 · 15 citations

Engineering, Electrical Engineering, Materials Science +17