3D copper TSV integration, testing and reliability

Mukta Farooq, Troy Graves-Abe, W. Landers, +16

3D Ic ArchitectureElectrical EngineeringEngineeringAdvanced Packaging (Semiconductors)Functional 3D +13

Solvent-enhanced dye diffusion in polymer thin films for polymer light-emitting diode application

Troy Graves-Abe, Florian Pschenitzka, H. Z. Jin, +3

Journal of Applied Physics

EngineeringOrganic ElectronicsLuminescence PropertySolvent-enhanced Dye DiffusionChemical Engineering +14

Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology

Pooja Batra, Spyridon Skordas, D. LaTulipe, +18

Journal of Low Power Electronics and Applications

EngineeringIntegrated CircuitsInterconnect (Integrated Circuits)Wafer Scale ProcessingAdvanced Packaging (Semiconductors) +14

Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias

T. Kirihata, John Golz, M.R. Wordeman, +6

IEEE Journal on Emerging and Selected Topics in Circuits and Systems

EngineeringEmerging Memory TechnologyComputer ArchitectureOrthogonal ScalingIntegrated Circuits +14

Submicron mapping of strain distributions induced by three-dimensional through-silicon via features

Conal E. Murray, Troy Graves-Abe, Robert R. Robison, +1

Applied Physics Letters

EngineeringX-ray Microbeam DiffractionMechanical EngineeringInteraction RegionIntegrated Circuits +19

Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate

K. Henson, H. Bu, Mulun Na, +35

EngineeringVlsi DesignPower ElectronicsGate Length ScalingSemiconductor Device +17

Bonding technologies for chip level and wafer level 3D integration

Katsuyuki Sakuma, Spyridon Skordas, Jeffrey A. Zitz, +15

EngineeringDevice IntegrationInterconnect (Integrated Circuits)Wafer Scale ProcessingAdvanced Packaging (Semiconductors) +15

Self-Aligned, Insulating-Layer Structure for Integrated Fabrication of Organic Self-Assembled Multilayer Electronic Devices

Troy Graves-Abe, Zhenan Bao, J. C. Sturm

Nano Letters

EngineeringOrganic ElectronicsMolecular Self-assemblyElectronic DevicesGold Film +19

Three-dimensional wafer stacking using Cu TSV integrated with 45nm high performance SOI-CMOS embedded DRAM technology

Pooja Batra, D. LaTulipe, Spyridon Skordas, +18

EngineeringComputer ArchitectureThree-dimensional WaferIntegrated CircuitsInterconnect (Integrated Circuits) +16

Prototype of multi-stacked memory wafers using low-temperature oxide bonding and ultra-fine-dimension copper through-silicon via interconnects

Wei‐Hung Lin, Johnathan Faltermeier, Kevin Winstel, +21

EngineeringComputer ArchitectureItrs RoadmapInterconnect (Integrated Circuits)Wafer Scale Processing +14