Pooja Batra

Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology

Pooja Batra, Spyridon Skordas, D. LaTulipe et al. · Journal of Low Power Electronics and Applications · 2014 · 19 citations · Full text

Engineering, Integrated Circuits, Interconnect (Integrated Circuits) +16

Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias

T. Kirihata, John Golz, M.R. Wordeman et al. · IEEE Journal on Emerging and Selected Topics in Circuits and Systems · 2016 · 18 citations

Engineering, Emerging Memory Technology, Computer Architecture +16

Three-dimensional wafer stacking using Cu TSV integrated with 45nm high performance SOI-CMOS embedded DRAM technology

Pooja Batra, D. LaTulipe, Spyridon Skordas et al. · 2013 · 13 citations

Engineering, Computer Architecture, Three-dimensional Wafer +18

Prototype of multi-stacked memory wafers using low-temperature oxide bonding and ultra-fine-dimension copper through-silicon via interconnects

Wei‐Hung Lin, Johnathan Faltermeier, Kevin Winstel et al. · 2014 · 11 citations

Engineering, Computer Architecture, Itrs Roadmap +16