Integration of trench DRAM into a high-performance 0.18 μm logic technology with copper BEOL

Abstract

In this work, we demonstrate the integration of trench DRAM into a 0.18 /spl mu/m copper BEOL technology which is fully compatible with our most advanced logic technology and requires no redesign of preexisting logic circuitry. This technology offers a 0.617 /spl mu/m/sup 2/ DRAM cell on the same chip as a 4.2 /spl mu/m/sup 2/ SRAM cell and dual damascene copper metallization with the highest reported device performance for a 1.5 V bulk silicon technology. We demonstrate a fixable retention time of over 256 ms at 85/spl deg/C for the DRAM cell without any degradation in logic device performance or density.