Capacitor-less, Long-Retention (>400s) DRAM Cell Paving the Way towards Low-Power and High-Density Monolithic 3D DRAM

Attilio Belmonte, Hyungrock Oh, Nouredine Rassoul, +18

Electrical EngineeringEngineeringTransistor Layout ParametersHigh-density Monolithic 3DScaled Transistor +13

Understanding and modelling the PBTI reliability of thin-film IGZO transistors

Adrian Chasin, J. Franco, K. Triantopoulos, +12

2021 IEEE International Electron Devices Meeting (IEDM)

EngineeringSemiconductor DeviceSemiconductorsDegradation ProcessPbti Reliability +14

Tailoring IGZO-TFT architecture for capacitorless DRAM, demonstrating > 10³s retention, >10¹¹ cycles endurance and L_g scalability down to 14nm

A. Belmonte, H. Oh, Subhali Subhechha, +19

2021 IEEE International Electron Devices Meeting (IEDM)

Electrical EngineeringCapacitorless DramEngineeringMemory ArchitectureIgzo-tft Architecture +11

Direct metal etch of ruthenium for advanced interconnect

Sara Paolillo, Danny Wan, Frédéric Lazzarino, +3

Journal of Vacuum Science & Technology B Nanotechnology and Microelectronics Materials Processing Measurement and Phenomena

EngineeringPattern TransferSolid-state ChemistryDirect Metal EtchPlasma Processing +15

Ultra-low Leakage IGZO-TFTs with Raised Source/Drain for V_t > 0 V and I_on > 30 µA/µm

Subhali Subhechha, Nouredine Rassoul, A. Belmonte, +21

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

Low-power ElectronicsElectrical EngineeringElectronic DevicesUltra-low Leakage Igzo-tftsEngineering +8

Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling

Anshul Gupta, Olalla Varela Pedreira, Goutham Arutchelvan, +54

IEEE Transactions on Electron Devices

EngineeringVlsi DesignIntegrated CircuitsInterconnect (Integrated Circuits)Advanced Packaging (Semiconductors) +14

Lowest I_OFF < 3×10⁻²¹ A/μm in capacitorless DRAM achieved by Reactive Ion Etch of IGZO-TFT

Attilio Belmonte, Shreya Kundu, Subhali Subhechha, +8

Active ModuleNon-volatile MemoryElectrical EngineeringCapacitorless DramIgzo-based 2T0c +12

Study of Contact Resistance Components in Short-Channel Indium-Gallium-Zinc-Oxide Transistor

Hongwei Tang, Harold Dekkers, Nouredine Rassoul, +7

IEEE Transactions on Electron Devices

Device ModelingSemiconductor TechnologyElectrical EngineeringElectronic DevicesEngineering +10

First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers

A. Vandooren, J. Franco, Zhicheng Wu, +30

EngineeringIntegrated CircuitsSequential Integration ApproachInterconnect (Integrated Circuits)Wafer Scale Processing +17

Subtractive Etch of Ruthenium for Sub-5nm Interconnect

Danny Wan, Sara Paolillo, Nouredine Rassoul, +9

Materials ScienceElectrical EngineeringMaterial AnalysisEngineeringEpitaxial Growth +12